{"id":9366,"date":"2026-10-14T15:36:52","date_gmt":"2026-10-14T07:36:52","guid":{"rendered":"https:\/\/www.akademisains.gov.my\/asmsj\/?post_type=article&p=9366"},"modified":"2026-10-14T15:36:52","modified_gmt":"2026-10-14T07:36:52","slug":"an-efficient-aes-128-cmos-architecture-with-round-reuse-and-composite-field-s-box-to-secure-iot-devices","status":"publish","type":"article","link":"https:\/\/www.akademisains.gov.my\/asmsj\/article\/an-efficient-aes-128-cmos-architecture-with-round-reuse-and-composite-field-s-box-to-secure-iot-devices\/","title":{"rendered":"An Efficient AES-128 CMOS Architecture with Round Reuse and Composite Field S-Box to Secure IoT Devices"},"content":{"rendered":"

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ASM Sc. J., 21(2), 2026<\/p>\r\n\t\t

Published on October 14, 2026<\/p>\r\n

https:\/\/doi.org\/10.32802\/asmscj.2026.1020<\/a><\/p>\r\n \r\n

Author: <\/strong>Salman Ahmed, Nabihah Ahmad, Chessda Uttraphan, Ardhi Wijayanto, Abdinasir Hirsi<\/p>\r\n \r\n

Abstract<\/strong><\/p>\r\n\t\t\t

The rapid growth of the Internet of Things (IoT) has intensified the demand for lightweight cryptographic solutions that deliver high security without compromising energy and area constraints. This paper presents a highly efficient AES -128 hardware architecture specifically optimised for resource-constrained IoT devices. The proposed design employs reusing a 128 -bit AES framework resource, enabling an extensive reduction in functional units across all transformation stages. Additionally, the elimination of intermediate registers and the reuse of a single round computation block for all encryption rounds significantly reduce area while balancing the trade -offs between throughput, frequency and power. A key innovation in this work is the implementation of a compact S-box using composite Galois Field GF28 arithmetic to enhance the substitution efficiency while maintaining cryptographic strength. The physical layout implemented on 32 nm technology reveals that the proposed architecture achieves a core area of only 0.015 \u202fmm , an operating \r\n2\r\nfrequency of 200 MHz, with 0.014 Gbps throughput, and a low power consumption of 1.4 mW , offering a well-balanced trade-off among performance, security, and hardware efficiency. A comparative analysis with state-of-the-art designs demonstrates the superiority of this approach for achieving low-cost, energy-aware cryptographic protection. The proposed solution is highly suitable for secure resource constrained IoT deployments.<\/p>\r\n \r\n

Keywords:<\/strong>\r\n Advanced encryption standard (AES), Application Specific Integrated Circuits (ASIC), Galois field (GF), Internet of Things (IoT), lightweight cryptography, Physical Layout Design, Substitution box (S-box) <\/p>\r\n <\/div>\r\n\t\r\n\t\r\n\t\r\n\t

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How to Cite<\/h3>\r\n

\r\n 2026. An Efficient AES-128 CMOS Architecture with Round Reuse and Composite Field S-Box to Secure IoT Devices. ASM Science Journal<\/em>, 21(2), 1-11. https:\/\/doi.org\/10.32802\/asmscj.2026.1020<\/a> <\/p>\r\n\r\n

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